From a59b0e652911627cb00b748bb71f07ce0fa90534 Mon Sep 17 00:00:00 2001
From: Steve Shenton <sgsit@libreboot.org>
Date: Fri, 12 Dec 2014 12:42:01 +0000
Subject: [PATCH] northbridge/gm45/raminit.c: enable GS45 high-performance mode

The datasheets for GS45 describe a high- and low-performance mode
for different CPUs. Coreboot currently disables GS45 altogether,
but forcing coreboot to treat high-performance GS45 as GM45 makes
the X200S and X200 Tablet boot if it has the right CPU type.

Hardcode-enable GS45 high-performance mode in coreboot, passing it
off as GM45. This is known to work with all CPUs except the SU
(low performance) models.

Change-Id: I57032bb6e1ebdaf4e2aa09548e73d253afb9b078
Signed-off-by: Steve Shenton <sgsit@libreboot.org>
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
---
 src/northbridge/intel/gm45/raminit.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 9c4fecd..9f5aa06 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -108,8 +108,8 @@ void get_gmch_info(sysinfo_t *sysinfo)
 			printk(BIOS_SPEW, "GMCH: GS40\n");
 			break;
 		case GMCH_GS45:
-			printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n");
-			sysinfo->gs45_low_power_mode = 1;
+			printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n");
+			sysinfo->gs45_low_power_mode = 0;
 			break;
 		case GMCH_PM45:
 			printk(BIOS_SPEW, "GMCH: PM45\n");
@@ -1692,7 +1692,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
 {
 	const dimminfo_t *const dimms = sysinfo->dimms;
 	const timings_t *const timings = &sysinfo->selected_timings;
-	const int sff = sysinfo->gfx_type == GMCH_GS45;
+	const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1);
 
 	int ch;
 	u8 reg8;
-- 
1.9.1

